As the semiconductor industry hit the 0.18-micron generation, it entered a new regime. For the first time, leading-edge device feature sizes became significantly smaller than the wavelength of light used by available best-in-class optical-lithography equipment. This shift to the subwavelength generation has had a dramatic impact on semiconductor manufacturing technology, and affects physical design at all levels-prompting design teams to scramble for the best solution to address the new subwavelength challenges.
Most leading-edge design teams do not have the time, the money or the desire, however, to hire or train experts on manufacturing technology to handle the impact of this new technique. Fortunately, with the appropriate design tools and methodologies, design teams can mitigate the effects of subwavelength technology and use the related performance improvements to their advantage.
This article will address the impact of subwavelength manufacturing on the design process, specifically at libraries, synthesis and physical design, and offer specific design-oriented solutions for embedding critical subwavelength information into the physical-design flow.
Both the 0.18-micron and 0.13-micron process generations use lithography equipment that utilizes a light wavelength of 248 nanometers-or approximately 0.25 micrometer-to pattern the features on an IC (Fig. 1). Each process generation contains features substantially smaller than the wavelength of that light. Under those conditions, optical distortions and other process effects deform the patterns, which are described in the design (GDS II) and printed onto a photomask, altering rectangle patterns into rounded, hourglass shapes and causing very fine features to disappear altogether.
This phenomenon translates into a serious manufacturing challenge. Line-width variations and other distortions can significantly decrease chip performance or, even worse, cause missing, incomplete or shorted structures that result in hard failure. Even if manufacturers absorb these failures, they pass yield problems along to their customers in the form of higher product costs and unreliable production delivery schedules. IC manufacturers are adopting nonequipment-based lithography technologies to combat the widening subwavelength gap. Optical proximity correction (OPC) and Numerical Technologies' proprietary phase-shifting technologies are by far the most common ones.
OPC and scattering bars are corrective lithography techniques that resolve distortions that result not only from optical proximity, but also from the diffusion and loading effects of resist and etch processing. The end goal of OPC is to improve device performance and yield (Fig. 2).
Subresolution OPC structures and scattering bars are added to layouts at the mask level to minimize the effects of optical and process distortions. Such corrections range from enhancing the outside corners of the design by adding tiny squares to prevent excessive rounding of required rectangles, to trimming the inside corners of geometries to prevent line shortening.
Phase-shifting technology uses optical interference to improve depth of focus and resolution in lithography. This optical interference is created by using ordinary chrome-on-glass masks to selectively change the phase of light used to expose IC features onto a wafer. Phase shifting enables significantly higher lithographic resolution and, hence, finer geometries (Fig. 3).
More of the same
An additional benefit of phase shifting is that it facilitates the creation of next-generation IC features using existing semiconductor process equipment and materials. This way, users can consistently and reliably shrink IC feature sizes to subwavelength geometries, providing a significant improvement in chip performance. As a result, phase shifting enables smaller feature sizes, improved yield (through tighter process control) and a dramatic extension of the useful life of current lithography equipment.
There are a variety of "flavors" of phase shifting, but several leading manufacturers are licensing and implementing the phase-shifting technology patented by Numerical Technologies.
In an example at Lucent Technologies, a 1.5-volt digital-signal-processing IC was fabricated on a 0.25-micron process, running at 60 MHz. After phase shifting, the same design produced 0.12-micron gates, ran at 170 MHz at 1.5 V (a near-3x improvement). The design ran at 100 MHz at 1 V.
Today, OPC and phase shifting are performed as a "point" basis after the design has already been completed.
Initially, this approach makes a great deal of sense, because design teams typically do not include a lithography expert. Nor should they have to. The lithographic aspect of these requirements might be of interest, but an IC designer's main goal is to complete the design. It is very important, however, that these effects be considered in the design process-as transparently as possible-and the answer lies in subwavelength-compliant tools and methodologies.
When subwavelength effects, OPC and phase shifting are not considered in the design process, there are problems that are flagged by the OPC and phase-shifting process. Resolving those can require substantial changes to the design. This means that the staff performing OPC and phase shifting must throw the design back to the design staff to resolve all the issues.
Those changes will have to be made at the physical-design stage, frequently accompanied by updates to library cells. A phase conflict that occurs within a NAND cell, for example, must be resolved in the library cell itself, rather than at every occurrence within the design. Both of those loops are very expensive, resource intensive and time-consuming, since if even one library cell needs to be updated, most of the design steps have to be repeated.
This approach may be acceptable to a microprocessor or a memory vendor, where the cost of the iterations can be amortized in large product volume. It is also more tolerable for an integrated device manufacturer, where the fab and design teams belong to the same company and this "throw back" can be accommodated. In a fabless COT market, however, these loops are too expensive for typical product volume to bear, and it is not common practice for foundries to just send the design back to the fabless design companies for correction. This "point" approach, therefore, is not realistic for the long term.
There are a number of examples where many of the requirements of subwavelength technologies must be handled up front in the IC design stage, while changes can still be made.
One example is the subwavelength proximity effects and how they affect IC design. Fig. 4 shows two SRAM bit cells. The bit cell on the left was designed with a less aggressive topology of elements in the cells. The area highlighted illustrates the predicted silicon image. As real estate is of ultimate importance to SRAM designers, an SRAM designer might want to push in the geometry in the bit cell to create a smaller bit cell (which will translate into a much smaller SRAM design).
The bit cell on the right shows a more aggressive topology. In this case, however, the silicon image indicates that there will be a number of shorts if this design is fabricated. The shorts are mostly due to the proximity of certain features. The proximity effects are by-products of the subwavelength gap and were not experienced to a great extent in the above-wavelength realm.
Having silicon simulation (a process described below) in hand, designers are able to correct for these extremely aggressive features while they can still make changes easily, instead of discovering them later on as manufacturing errors.
Another example is a phase conflict. Phase conflicts are areas where locations that are reserved for phase shifters of opposite phase overlap, resulting in a misprinted feature. Resolving phase conflicts is a full-chip challenge-in other words, resolving a phase conflict in one corner of the design might force a phase conflict on another corner. There are many ways to resolve phase conflicts, but they all require making adjustments to spacing and the topology of the design. The most efficient stage at which to make these adjustments is during the physical-design process-not the tapeout process.
The impact of phase shifting on performance is another good example. Fig. 5 illustrates the effects of phase shifting on the overall timing of the devices in a design. The red curve shows the delay distribution for a design, and the green curve shows the delay distribution for the same design after phase shifting and OPC have been applied to the final design. During the design process, the logic synthesis and timing-analysis steps were performed using delay information based on the red curve. The actual chip itself, however, will behave with primitive delay information corresponding to the green curve.
There are two problems with this approach. First, the designer has forsaken a great deal of performance by not taking the faster-performance profile into account; and worse, the application of phase shifting as a post-design process almost guarantees a number of setup-and-hold violations, as well as racing conditions and clock skew problems that were unaccounted for.
The only way to ensure these problems are dealt with is to take into account the effects and requirements of phase shifting in library characterization, logic synthesis and timing analysis. To best address those challenges, it is very important to employ the entire design methodology for subwavelength manufacturing. The following technologies should be embedded into existing design tools in an integrated and transparent fashion: silicon simulation, intelligent OPC, phase-smart physical design and subwavelength-enabled system-on-chip (SoC) intellectual property (IP) and custom blocks.
Silicon simulation
Silicon simulation is the capability to predict the pattern printed on silicon for a given layout. This is a complex task, as there are many factors in IC manufacturing that influence a silicon image, including original layout, mask process, stepper optics, photoresist characteristics, and develop and etch steps. Silicon simulation takes into account the impact of all these steps and characteristics on layout, and produces a simulated printed pattern that predicts what the layout would look like in silicon, without having to go through the costly and time-consuming manufacturing process.
One of the applications using silicon simulation is silicon vs. layout verification, which uses simulation to compare the silicon "image" against the ideal "drawn" layout. Due to the nature of subwavelength issues, the last step in every subwavelength design must be silicon vs. layout verification.
Today, there are several valid "insertion points" for applying OPC. Most people apply OPC at the end of the design cycle, once the design is entirely completed. This allows the OPC process for each geometry to take the proximity effects from all neighboring geometries into account and correct accordingly. Nevertheless, there are other design practices where OPC is embedded in the SoC IP (such as standard-cell libraries) or in the bit cells of embedded memories in order to ensure high manufacturing yield or performance tuning. It is also very conceivable that OPC may be done at different points during the design flow, depending on the nature of the block.
Subwavelength design methodologies and tools should provide OPC capability in many different points during design flow, including at library creation; at custom-block creation; during integration of blocks; at physical verification; and during mask data preparation. Also, these tools should support such different styles of OPC as automatic vs. manual, rules-based, model-based and hybrid, and simple vs. aggressive corrections. And the tools should be flexible for integration of portions with different types and levels of OPC. (For example, one has the option to modify output hierarchy or keep it the same as input hierarchy.)
Only through this flexible design methodology can the optimal level of OPC be applied to meet the performance, manufacturing-yield and mask-manufacturing requirements of the design.
Phase-smart physical design requires a physical-design environment (consisting of methodology and tools) that handles phase conflicts on a global and local scale, on the fly and in a transparent manner. The goal of phase-smart design is to produce layouts that do not have any phase conflicts, and therefore guarantee success in manufacturing the corresponding mask set.
To that end, a phase-smart physical-design tool must first detect possible phase conflicts that exist in the layout and transparently resolve them. By the same token, if an operation in any of these phase-smart tools were to cause a phase conflict anywhere in the layout, the conflict would automatically be identified and avoided.
Furthermore, since physical-design tools also take timing into consideration (such as timing-driven placement), phase-smart physical-design tools must also take into account the effects of phase shifting on timing whenever applicable.
Tight links
Developing these tools is not a trivial task. The phase-conflict and "coloring" algorithms are complex, and designers should look for tools that are tightly linked to technology approaches and to rules dictated by manufacturing. Let's take the standard-cell design methodology as an example.
Phase conflicts could arise in two ways: within each cell (intracell) and between two neighboring cells (intercell). They could occur in the form of four common types: 1) intracell; 2) between abutting cells in the same row; 3) between abutting cells in two adjacent rows; and 4) a combination of 2 and 3 (Fig. 6).
The goal of the phase-smart standard-cell place and route tool is to consider manufacturing issues, resolve possible phase conflicts and produce a phase-shiftable final design that eliminates expensive iteration between mask/silicon manufacturing and design teams.
To remove phase conflicts in a standard-cell physical-design flow, the following strategy is used:
Remove possible intracell phase conflicts,
Remove possible intercell phase conflicts,
Verify DRC and phase correctness.
Resolution and removal of intracell phase conflicts is mainly a function of standard-cell library or custom-block creation. Also, certain intercell phase conflicts can be minimized or, optimally, removed through intelligent library design.
Phase conflicts can be avoided by considering cell development rules or guidelines that will help reduce the possibility of phase conflicts. These include guidelines determined by considering minimum spacing requirements between phase shifters, odd cycles, placement and routing.
Furthermore, the selection of an appropriate cell architecture will reduce the possibility of-or even remove-intercell phase conflicts. Designers who choose to have power rails (e.g., Metal 1 layer) on the top and bottom side of the cells will completely eliminate the possibility of intercell phase conflicts in abutting cells between two adjacent rows in the poly layer.
Placement and routing resolve the remaining intercell phase conflicts. A phase-smart place and route tool, while treating cells as "abstracts" or "black boxes," will recognize which cell abutments will create phase conflicts, and will either avoid placement of those cells altogether, space them or move them to different locations in the same row or to different rows.
Finally, once phase conflicts are resolved, silicon simulation is used within three components. The first is silicon visualization, in which the layout designer sees the silicon equivalent of every polygon drawn and uses that to perform manual OPC and make final manufacturing-driven touch-ups. Next is silicon image extraction (as opposed to the ideal design data extraction) for accurate device and parasitic information fed back for final timing analysis. Last is silicon vs. layout verification, to verify both phase correction and manufacturability of any OPC that was performed.
Silicon image extraction is highly critical for accurate device and parasitic extraction, especially as more analog, mixed-signal and RF elements are being added to designs, and as parameter matching and inductance modeling play a greater role in meeting design performance goals.
To succeed under today's industry conditions, accommodations must be made in libraries, SoC IP and custom blocks to enable designers to use them transparently.
Subwavelength processes, including phase shifting, OPC and related silicon effects and modeling, are incorporated into the design process through these libraries.
This is also the most effective way to make subwavelength techniques transparent, since the subwavelength effects are then modeled correctly through many library views for synthesis, place and route, timing simulation and verification. In order to meet phase-conflict requirements for subwavelength manufacturing at the library level, a number of variables must be met, including the elimination of phase conflicts within the cells; the elimination or minimization of potential phase conflicts between the cells; subwavelength cell layout development rules; and the use of those rules working in conjunction with phase-smart place and route. At the end, these libraries and other SoC IP and custom blocks must all be characterized using transistor Spice models. The models must correspond to the manufacturing techniques used as well as capture the effects of those techniques on the performance of transistors.
Automation plays a strong role in accomplishing these highly technical and highly concurrent tasks. Cell layout complexity significantly increases with subwavelength technologies to account for the following: type 1, type 2 and type 3 rules; handling intracell phase conflicts; and management of intercell phase-conflict resolution through the place and route tool.
Additionally, highly context-sensitive treatment of layout increases cell layout complexity. Optical-lithography analysis and knowledge requirements further drive cell layout complexity. Those requirements cannot all be represented as global rules, and, therefore, even a complicated design rule check (DRC) is not capable of verifying the correctness of the cells. The most reasonable way to account for this level of complexity is through automation.
Designers can then reliably access phase-shifting technology for the 0.13-micron generation with a minimal amount of effort by using phase-compliant standard cells, embedded memory and SoC IP cores. Using a phase-compliant standard-cell library, designers can ensure that no phase conflicts are created as they apply synthesis and place and route.
Ultimately, they can ensure that the final design is phase-shift compliant, and that the resulting chip performance meets expectations.
---
As director of marketing and business development for IC design at Numerical Technologies (San Jose, Calif.), Michael Sanie manages design products and IC/EDA company partnerships. He holds an MBA from Santa Clara University and an MEE from Purdue University.
http://www.isdmag.com
Copyright © 2002 CMP Media LLC
2/1/02, Issue # 14152, page 20.
